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19-1768; Rev 1; 4/09
Dual Universal Switched-Capacitor Filters
General Description
The MAX7490/MAX7491 consist of two identical lowpower, low-voltage, wide dynamic range, rail-to-rail, 2nd-order switched-capacitor building blocks. Each of the two filter sections, together with two to four external resistors, can generate all standard 2nd-order functions: bandpass, lowpass, highpass, and notch (band reject). Three of these functions are simultaneously available. Fourth-order filters can be obtained by cascading the two 2nd-order filter sections. Similarly, higher order filters can easily be created by cascading multiple MAX7490/MAX7491s. Two clocking options are available: self-clocking (through the use of an external capacitor) or external clocking for tighter cutoff frequency control. The clockto-center frequency ratio is 100:1. Sampling is done at twice the clock frequency, further separating the cutoff frequency and Nyquist frequency. The MAX7490/MAX7491 have an internal rail splitter that establishes a precise common voltage needed for single-supply operation. The MAX7490 operates from a single +5V supply and the MAX7491 operates from a single +3V supply. Both devices feature a low-power shutdown mode and come in a 16-pin QSOP package.
Features
o Dual 2nd-Order Filter in a 16-Pin QSOP Package o High Accuracy Q Accuracy: 0.2% Clock-to-Center Frequency Error: 0.2% o Rail-to-Rail Input and Output Operation o Single-Supply Operation: +5V (MAX7490) or +3V (MAX7491) o Internal or External Clock o Highpass, Lowpass, Bandpass, and Notch Filters o Clock-to-Center Frequency Ratio of 100:1 o Internal Sampling-to-Center Frequency Ratio of 200:1 o Center Frequency up to 40kHz o Easily Cascaded for Multipole Filters o Low-Power Shutdown: < 1A Supply Current
MAX7490/MAX7491
Ordering Information
PART MAX7490CEE+ MAX7490EEE+ MAX7491CEE+ TEMP RANGE 0C to +70C -40C to +85C 0C to +70C SUPPLY PINVOLTAGE PACKAGE (+V) 16 QSOP 16 QSOP 16 QSOP 5 5 3 3
________________________Applications
Tunable Active Filters Multipole Filters ADC Anti-Aliasing Post-DAC Filtering Adaptive Filtering Phase-Locked Loops (PLLs) Set-Top Boxes
MAX7491EEE+ -40C to +85C 16 QSOP +Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configuration
TOP VIEW
LPA 1 BPA 2 NA/HPA 3
+
16 LPB 15 BPB 14 NB/HPB
Typical Application Circuit appears at end of data sheet.
INVA 4 SA 5 SHDN 6 GND 7 VDD 8
MAX7490 MAX7491
13 INVB 12 SB 11 COM 10 EXTCLK 9 CLK
QSOP ________________________________________________________________ Maxim Integrated Products
1
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Dual Universal Switched-Capacitor Filters MAX7490/MAX7491
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V EXTCLK, SHDN to GND ...........................................-0.3V to +6V INV_, LP_, BP_, N_/HP_, S_, COM, CLK to GND............................................-0.3V to (VDD + 0.3V) Maximum Current into Any Pin ...........................................50mA Continuous Power Dissipation (TA = +70C) 16-Pin QSOP (derate 8.30mW/C above +70C).........667mW Operating Temperature Range MAX749_CEE .....................................................0C to +70C MAX749_EEE ...................................................-40C to +85C Die Temperature ..............................................................+150C Storage Temperature.........................................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS--MAX7490
(VDD = VEXTCLK = +5V; fCLK = 625kHz; 10k || 50pF load to VDD/2 at LP_, BP_, and N_/HP_; VSHDN = VDD; 0.1F from COM to GND; 50% duty-cycle clock input; COM = VDD/2; TA = TMIN to TMAX. Typical values are at TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER FILTER Center Frequency Range Clock-to-Center Frequency Accuracy Q Accuracy fO Temperature Coefficient Q Temperature Coefficient DC Lowpass Gain Accuracy VOS1 DC Offset Voltage (Figure 8) Crosstalk (Note 2) VOS2 VOS3 Mode 1, R1 = R2 = 10k DC offset of input inverter DC offset of 1st integrator DC offset of 2nd integrator fIN = 10kHz Input: COM externally driven COM Voltage Range VCOM Output: COM internally driven Input Resistance at COM Clock Feedthrough Noise (Note 3) Output Voltage Swing Input Leakage Current at COM CLOCK Maximum Clock Frequency Internal Oscillator Frequency (Note 4) Clock Input High fCLK fOSC EXTCLK = GND, COSC = 1000pF EXTCLK = GND, COSC = 100pF VDD - 0.5 95 4 135 1.35 175 MHz kHz MHz V SHDN = GND, VCOM = 0 to VDD RCOM Up to 5th harmonic of fCLK Mode 1, R1 = R2 = R3 =10k, LP output, Q=1 0.2 0.1 VDD/2 - 0.5 VDD/2 - 0.2 140 fO fCLK/fO Mode 1 Mode 1, R1 = R3 = 50k , R2 = 10k, Q = 5, deviation from 100:1 Mode 1, R1 = R3 = 50k, R2 = 10k, Q = 5 0.001 to 40 0.2 0.2 1 5 0.1 3 4 4 -60 VDD/2 VDD/2 250 200 60 VDD - 0.2 10 VDD/2 + 0.5 V VDD/2 + 0.2 325 k VRMS VRMS V A 0.5 12.5 15 30 dB mV 0.7 2 kHz % % ppm/C ppm/C % SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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Dual Universal Switched-Capacitor Filters
ELECTRICAL CHARACTERISTICS--MAX7490 (continued)
(VDD = VEXTCLK = +5V; fCLK = 625kHz; 10k || 50pF load to VDD/2 at LP_, BP_, and N_/HP_; VSHDN = VDD; 0.1F from COM to GND; 50% duty-cycle clock input; COM = VDD/2; TA = TMIN to TMAX. Typical values are at TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Clock Input Low Clock Duty Cycle SHDN AND EXTCLK Input High Input Low Input Leakage Current POWER REQUIREMENTS Supply Voltage Power-Supply Current Shutdown Current VDD IDD ISHDN No external load, mode 1, R1 = R3 = 50k, R2 = 10k, Q = 5 SHDN = GND 18 RL 10k, CL 50pF GBW SR RL 10k, CL 50pF RL 10k, CL 50pF 130 7 6.4 4.5 3.5 5.5 4.0 1 V mA A mA dB MHz V/s VIH VIL VINPUT = 0 to VDD 0.4 VDD - 0.5 0.5 10 V V A 50 5 SYMBOL CONDITIONS MIN TYP MAX 0.5 UNITS V %
MAX7490/MAX7491
INTERNAL OP AMPS CHARACTERISTICS Output Short-Circuit Current DC Open-Loop Gain Gain Bandwidth Product Slew Rate
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Dual Universal Switched-Capacitor Filters MAX7490/MAX7491
ELECTRICAL CHARACTERISTICS--MAX7491
(VDD = VEXTCLK = +3V; fCLK = 625kHz; 10k || 50pF load to VDD/2 at LP_, BP_, and N_/HP_; VSHDN = VDD; 0.1F from COM to GND; 50% duty-cycle clock input; COM = VDD/2; TA = TMIN to TMAX. Typical values are at TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER FILTER Center Frequency Range Clock-to-Center Frequency Accuracy Q Accuracy fO Temperature Coefficient Q Temperature Coefficient DC Lowpass Gain Accuracy DC Offset Voltage (Figure 8) Crosstalk (Note 2) VOS1 VOS2 VOS3 Mode 1, R1 = R2 = 10k DC offset of input inverter DC offset of 1st integrator DC offset of 2nd integrator fIN = 10kHz Input: COM externally driven COM Voltage Range VCOM Output: COM internally driven Input Resistance at COM Clock Feedthrough Noise (Note 3) Output Voltage Swing Input Leakage Current at COM CLOCK Maximum Clock Frequency Internal Oscillator Frequency (Note 4) Clock Input High Clock Input Low Clock Duty Cycle SHDN AND EXTCLK Input High Input Low Input Leakage Current VIH VIL VINPUT = 0 to VDD 0.4 VDD - 0.5 0.5 10 V V A 50 5 fCLK fOSC EXTCLK = GND, COSC = 1000pF EXTCLK = GND, COSC = 100pF VDD - 0.5 0.5 95 4 135 1.35 175 MHz kHz MHz V V % SHDN = GND, VCOM = 0 to VDD RCOM Up to 5th harmonic of fCLK Mode 1, R1= R2 = R3 = 10k, LP output, Q = 1 0.2 0.1 VDD/2 - 0.1 VDD/2 - 0.1 60 fO fCLK/fO Mode 1 Mode 1, R1 = R3 = 50k , R2 = 10k, Q = 5, deviation from 100:1 Mode 1, R1 = R3 = 50k, R2 = 10k, Q=5 0.001 to 40 0.2 0.2 1 5 0.1 3 4 4 -60 VDD/2 VDD/2 80 200 60 VDD - 0.2 10 VDD/2 + 0.1 V VDD/2 + 0.1 120 k VRMS VRMS V A 0.5 12.5 15 25 dB mV 0.7 2 kHz % % ppm/C ppm/C % SYMBOL CONDITIONS MIN TYP MAX UNITS
4
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Dual Universal Switched-Capacitor Filters MAX7490/MAX7491
ELECTRICAL CHARACTERISTICS--MAX7491 (continued)
(VDD = VEXTCLK = +3V; fCLK = 625kHz; 10k || 50pF load to VDD/2 at LP_, BP_, and N_/HP_; VSHDN = VDD; 0.1F from COM to GND; 50% duty-cycle clock input; COM = VDD/2; TA = TMIN to TMAX. Typical values are at TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER POWER REQUIREMENTS Supply Voltage Power-Supply Current Shutdown Current Output Short-Circuit Current DC Open-Loop Gain Gain Bandwidth Product Slew Rate GBW SR RL 10k, CL 50pF RL 10k, CL 50pF RL 10k, CL 50pF VDD IDD ISHDN No load, mode 1, R1 = R3 = 50k, R2 = 10k, Q = 5 SHDN = GND 11 130 7 6 2.7 3.5 3.6 4.0 1 V mA A mA dB MHz V/s SYMBOL CONDITIONS MIN TYP MAX UNITS
INTERNAL OP AMPS CHARACTERISTICS
Note 1: Resistive loading of the N_/HP_, LP_, BP_ outputs includes the resistors used for the filter implementation. Note 2: Crosstalk between internal filter sections is measured by applying a 1VRMS 10kHz signal to one bandpass filter section input and grounding the input of the other bandpass filter section. The crosstalk is the ratio between the output of the grounded filter section and the 1VRMS input signal of the other section. Note 3: Bandwidth of noise measurement is 80kHz. Note 4: fOSC (kHz) = 135 x 103 / COSC (COSC in pF)
Typical Operating Characteristics
(VDD = +5V for MAX7490, VDD = +3V for MAX7491, fCLK = 625kHz, VSHDN = VEXTCLK = VDD, COM = VDD/2, Mode 1, R3 = R1 = 50k, R2 = 10k, Q = 5, TA = +25C, unless otherwise noted.)
2ND-ORDER BANDPASS FILTER FREQUENCY RESPONSE
MAX7490-01
2ND-ORDER BANDPASS FILTER PHASE RESPONSE
MAX7490-02
CLOCK-TO-CENTER FREQUENCY DEVIATION vs. CLOCK FREQUENCY
-0.1 fCLK/fO DEVIATION (%) -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 VDD = 5V VDD = 3V
MAX7490-03
10 0 -10 -20 -30 -40 -50 -60 1 10 FREQUENCY (kHz)
300 250 200 PHASE (%) 150 100 50 0 VDD = +5V fCLK = 625kHz Q=5 1 10 FREQUENCY (kHz)
0
GAIN (dB)
100
100
100
1000 fCLK (kHz)
10,000
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Dual Universal Switched-Capacitor Filters MAX7490/MAX7491
Typical Operating Characteristics (continued)
(VDD = +5V for MAX7490, VDD = +3V for MAX7491, fCLK = 625kHz, VSHDN = VEXTCLK = VDD, COM = VDD/2, Mode 1, R3 = R1 = 50k, R2 = 10k, Q = 5, TA = +25C, unless otherwise noted.)
CLOCK-TO-CENTER FREQUENCY DEVIATION vs. Q
MAX7490-04
CLOCK-TO-CENTER FREQUENCY DEVIATION vs. TEMPERATURE
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -40 -15 10 35 60 TEMPERATURE (C)
MAX7490-05
Q DEVIATION vs. CLOCK FREQUENCY
VDD = 5V 0 -1 Q DEVIATION (%) -2 -3 -4 -5 -6 85 100 1000 fCLK (kHz) 10,000 VDD = 3V
MAX7490-06
0.2 VDD = 5V 0.1 fCLK/fO DEVIATION (%) 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 0 20 40 Q 60 80 VDD = 3V
1
100
Q DEVIATION vs. TEMPERATURE
MAX7490-07
fCLK/fO DEVIATION (%)
NOISE vs. Q
MAX7490-08
SUPPLY CURRENT vs. TEMPERATURE
MAX7490-09
2.0 1.5 1.0 Q DEVIATION (%) 0.5 0 -0.5 -1.0 -1.5 -2.0 -40 -15 10 35 60
500 450 400 350 NOISE (VRMS)
3.7 3.6 3.5 IDD (mA) 3.4 3.3 3.2 3.1 3.0 VDD = 5V VDD = 3V
300 250 200 150 100 50 0
85
0
20
40 Q
60
80
100
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX7490-10
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX7490-11
MAX7491 THD + NOISE vs. FREQUENCY
-30 -40 A = MODE 1 B = MODE 3
MAX7490-12
4.0 3.9 3.8 3.7 IDD (mA) 3.6 3.5 3.4 3.3 3.2 3.1 3.0 3.0 3.5 4.0 4.5 5.0 fCLK = 2kHz fCLK = 625kHz fCLK = 3MHz
3.41 3.40 3.39 +85C
-20
THD + NOISE (dB)
3.38 IDD (mA) 3.37 3.36 3.35 3.34 3.33 3.32 5.5 3.0 3.5 4.0 4.5 5.0 5.5 -40C +25C
-50 -60 -70 -80 -90 -100 -110 -120 1k INPUT FREQUENCY (Hz) 10k B A
VDD (V)
VDD (V)
6
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Dual Universal Switched-Capacitor Filters MAX7490/MAX7491
Typical Operating Characteristics (continued)
(VDD = +5V for MAX7490, VDD = +3V for MAX7491, fCLK = 625kHz, VSHDN = VEXTCLK = VDD, COM = VDD/2, Mode 1, R3 = R1 = 50k, R2 = 10k, Q = 5, TA = +25C, unless otherwise noted.)
MAX7490 THD + NOISE vs. FREQUENCY
MAX7490-13
MAX7491 THD + NOISE vs. INPUT VOLTAGE
MAX7490-14
MAX7490 THD + NOISE vs. INPUT VOLTAGE
-20 -30 THD + NOISE (dB) -40 -50 -60 -70 B A 0 1 2 3 4 5 A = MODE 1 B = MODE 3
MAX7490-15
-20 -30 -40 THD + NOISE (dB)
A = MODE 1 B = MODE 3
-10 -20 -30 THD + NOISE (dB) -40 -50 -60 B -70 -80 -90 A
A = MODE 1 B = MODE 3
-10
-50 -60 -70 -80 -90 -100 -110 -120 1k INPUT FREQUENCY (Hz) 10k B A
-80 -90 1.5 2.0 2.5 3.0
0
0.5
1.0
INPUT VOLTAGE (Vp-p)
INPUT VOLTAGE (Vp-p)
OUTPUT VOLTAGE SWING vs. LOAD RESISTANCE
MAX7490-16
INTERNAL OSCILLATOR PERIOD vs. SMALL CAPACITANCE
INTERNAL OSCILLATOR FREQUENCY (kHz)
MAX7490-17
INTERNAL OSCILLATOR PERIOD vs. LARGE CAPACITANCE
INTERNAL OSCILLATOR FREQUENCY (kHz) 140 120 100 80 60 40 20 0 1 2 3 4 5 6 7 VDD = 5V VDD = 3V
MAX7490-18
5.0 4.5 OUTPUT SWING (Vp-p) 4.0 3.5 3.0 2.5 2.0 0 4 8 12 16
2500
160
VDD = 5V
2000
1500
VDD = 3V
1000
VDD = 3V
500 VDD = 5V 0 0 200 400 600 800 1000
20
RLOAD (k) TO COM
CAPACITANCE (pF)
CAPACITANCE (nF)
INTERNAL OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE
MAX7490-19
INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE
INTERNAL OSCILLATOR FREQUENCY (kHz) 142 140 138 136 134 132 130 128 126 124 -40 -15 10 35 60 85 VDD = 5V VDD = 3V COSC = 1000pF
MAX7490-20
133 INTERNAL OSCILLATOR FREQUENCY (kHz) 132 131 130 129 128 127 126
144
COSC = 1000pF
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
TEMPERATURE (C)
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Dual Universal Switched-Capacitor Filters MAX7490/MAX7491
Pin Description
NAME PIN FILTER A LP_ BP_ N_/HP_ INV_ 1 2 3 4 FILTER B 16 15 14 13 2nd-Order Lowpass Filter Output 2nd-Order Bandpass Filter Output 2nd-Order Notch/Highpass Filter Output Inverting Input of Filter Summing Op Amp Summing Input. The connection of the summing input, along with the other resistor connections, determine the circuit topology (mode) of each 2ndorder section. S_ must never be left unconnected. Shutdown Input. Drive SHDN low to enable shutdown mode; drive SHDN high or connect to VDD for normal operation. Ground Pin Positive Supply. Bypass VDD with a 0.1F capacitor to GND. A low-noise supply is recommended. Input +5V for MAX7490 or +3V for MAX7491. Clock Input. Connect CLK to an external capacitor (COSC) between CLK and ground to set the internal oscillator frequency. For external clock operation, drive CLK with a CMOS-level clock. The duty cycle of the external clock should be between 45% and 55% for best performance. External/Internal Clock Select Input. Connect EXTCLK to VDD when driving CLK externally. Connect EXTCLK to GND when using the internal oscillator. Common Pin. Biased internally at VDD/2. Bypass externally to GND with 0.1F capacitor. To override the internal biasing, drive COM with an external low-impedance source. FUNCTION
S_
5
12
SHDN GND VDD
6 7 8
CLK
9
EXTCLK
10
COM
11
_______________Detailed Description
The MAX7490/MAX7491 are universal switched-capacitor filters designed with a fixed internal fCLK/fO ratio of 100:1. Operating modes use external resistors connected in different arrangements to realize different filter functions (highpass, lowpass, bandpass, notch) in all of the classical filter topologies (Butterworth, Bessel, elliptic, Chebyshev). Figure 1 shows a block diagram.
the external clock adjusts the center frequency of the filter: fO = fCLK /100
Clock Signal
External Clock The MAX7490/MAX7491 switched-capacitor filters are designed for use with external clocks that have a 50% 5% duty cycle. When using an external clock, drive the EXTCLK pin high or connect to VDD. Drive CLK with CMOS logic levels (GND and VDD). Varying the rate of
Internal Clock When using the internal oscillator, drive the EXTCLK pin low or connect to GND and connect a capacitor (COSC) between CLK and GND. The value of the capacitor (COSC) determines the oscillator frequency as follows: fOSC (kHz) = 135 x 103 / COSC (pF) Since COSC is in the low picofarads, minimize the stray capacitance at CLK so that it does not affect the internal oscillator frequency. Varying the frequency of the internal oscillator adjusts the filter's center frequency by a 100:1 clock-to-center frequency ratio. For example, an internal oscillator frequency of 135kHz produces a nominal center frequency of 1.35kHz.
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Dual Universal Switched-Capacitor Filters MAX7490/MAX7491
(6)
SHDN
VDD (8)
INVA (4) R
NA/HPA (3)
BPA (2)
LPA (1)
+
-
BPB (15)
LPB (16)
COM (11) NB/HPB (14) SA (5)
R INVB (13) GND (7) CLK (9) EXTCLK (10)
+
SB (12)
Figure 1. Block Diagram
2nd-Order Filter Stage
The MAX7490/MAX7491 are dual biquad filters. The biquad topology allows the use of standard filter tables and equations to implement simultaneous lowpass, bandpass, and notch or highpass filters. Topologies such as Butterworth, Chebyshev, Bessel, elliptic, as well as custom algorithms are possible.
notch (band-reject) functions. Three of these functions are simultaneously available. The maximum signal swing is limited by the power-supply voltages used. The amplifiers' outputs in the MAX7490/MAX7491 are able to swing to within approximately 0.2V of either supply. Driving coaxial cable, large capacitive loads, or total resistive loads less than 10k will degrade the total harmonic distortion (THD) performance. Note that the effective resistive load at the output must include both the feedback resistors and any external load resistors.
Internal Common Voltage
The COM pin sets the common-mode input voltage and is internally biased to VDD/2 with a resistor-divider. The resistors used are typically 250k for the MAX7490, and typically 80k for the MAX7491. The commonmode voltage is easily overdriven by an external voltage supply if desired. Bypass COM to the analog ground with at least a 0.1F capacitor.
Low-Power Shutdown Mode
The MAX7490/MAX7491 have a shutdown mode that is activated by driving SHDN low. In shutdown mode, the filter supply current reduces to < 1A (max), and the filter outputs become high impedance. The COM input also becomes high impedance during shutdown. For normal operation, drive SHDN high or connect to VDD.
Inverting Inputs
Locate resistors that are connected to INV_ as close as possible to INV_ to reduce stray capacitance and noise pickup. INV_ are inverting inputs to continuous-time op amps, and behave like a virtual ground. There is no sampling energy present on these inputs.
__________Applications Information
Designing with the MAX7490/MAX7491 begins by selecting the mode that best fits the desired circuit requirements. Table 1 lists the available modes and their relative advantages and disadvantages. Table 2 lists the different nomenclature used in the explanations that follow.
Outputs
Each switched-capacitor section, together with two to four external resistors, can generate all standard 2ndorder functions: bandpass, lowpass, highpass, and
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Dual Universal Switched-Capacitor Filters MAX7490/MAX7491
Table 1. Filter Operating Modes
MODE LP * HP BP * N * LP-N* HP-N* COMMENTS fCLK/fO ratio is the nominal value. Good for bandpass filters with identical sections cascaded, higher order Butterworth filters, high-Q bandpass, low-Q notches. Same as Mode 1 with fCLK/fO ratios greater than the nominal value. Combination of Mode 1 and Mode 3; fCLK/fO ratios always less than the nominal value. Less sensitivity to resistor tolerances than Mode 3. * Extension of Mode 2 that allows higher frequencies. Highpass and lowpass outputs are summed with external op amp and two resistors. Good for lowpass elliptic filters. Adjustable fO above and below the nominal frequency. Commonly used for multiple-pole Chebyshev filters, all-pole higher order bandpass, lowpass, and highpass filters. * * Extension of Mode 3 that needs an external op amp and two additional resistors. Commonly used for lowpass or higher elliptic or Cauer filters.
1
1B
*
*
*
2
*
*
*
2N
3
*
*
*
3A
*
*
*
*LP-N = lowpass notch, HP-N = highpass notch. Both require an external op amp. See Definition of Terms (Table 2).
Table 2. Definition of Terms
TERM fCLK fO fNOTCH Q HOBP HOLP HOHP HON1 HON2 LP-N HP-N DEFINITION The clock frequency applied to the switched-capacitor filter. The center frequency of the 2nd-order complex pole pair, fO, is determined by measuring the peak response frequency at the bandpass output. The frequency of minimum amplitude response at the notch output. Quality factor, or Q, is the ratio of fO to the -3dB bandwidth of the 2nd-order bandpass filter. Q also determines the amount of amplitude peaking at the lowpass and highpass outputs, but is not measured at these outputs. The gain in V/V of the bandpass output at f = fO. The gain in V/V of the lowpass output at f0Hz. The gain in V/V of the highpass output at ffCLK/2. The notch output gain as f0Hz. The notch output gain at f = fCLK/2. A notch output with HON1 > HON2. A notch output with HON1 < HON2.
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Dual Universal Switched-Capacitor Filters MAX7490/MAX7491
CC R3
R3 R6 COM CC R5
R2 N R1 VIN S BP LP
R1 R2
N
S
BP
LP
+
-
VIN
+
-
COM
COM
Figure 2. Mode 1, 2nd-Order Filter Providing Notch, Bandpass, and Lowpass Outputs
Figure 3. Mode 1B, 2nd-Order Filter Providing Notch, Bandpass, and Lowpass Outputs
Mode 1 Figure 2 shows the MAX7490/MAX7491s' configuration of Mode 1. This mode provides 2nd-order notch, lowpass, and bandpass filter functions. The gain at all three outputs is inversely proportional to the value of R1. The center frequency, fO, is fixed at fCLK/100. HighQ bandpass filters can be built without exceeding the bandpass amplifier's output swing (i.e., HOBP does not have to track Q). The notch and bandpass center frequencies are identical. The notch output gain is the same above and below the notch center frequency. Mode 1 can also be used to make high-order Butterworth lowpass filters, low Q notches, and multiple-order bandpass filters obtained by cascading identical switched-capacitor sections. Mode 1 Design Equations
f fO = CLK 100 fnotch = fO R3 Q= R2 -R2 HOLP = R1 -R 3 HOBP = R1 HON1(as f 0Hz) =
-R2
Mode 1B Figure 3 shows the configuration of Mode 1B. R5 and R6 are added to lower the feedback voltage from the lowpass output to the summing input. This allows the clock-to-center frequency to be adjusted beyond the nominal value. This mode essentially has the same functions and speed as Mode 1 while providing a highQ with fCLK/fO ratios greater than the nominal value. Mode 1B Design Equations
f fO = CLK 100 fn = fO Q= R3 R2 R6 R6 + R5 R6
-R2
HOLP = HOBP =
R6 + R5 R6 + R5 R6
R1
-R 3
R1
-R2
HON1(as f 0Hz) =
R1
-R2
HON2 (at f = fCLK / 2) =
R1
R1
-R2
HON2 (at f = fCLK / 2) =
R1
Mode 2 Figure 4 shows the configuration of Mode 2. Mode 2 is a combination of Mode 1 and Mode 3. In this mode, fCLK/fO is always less than the part's nominal ratio. However, it provides less sensitivity to resistor tolerances than does Mode 3. It has a highpass notch output where the notch frequency depends solely on the clock frequency.
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Dual Universal Switched-Capacitor Filters MAX7490/MAX7491
Mode 2 Design Equations f fO = CLK 100 fCLK fn = 100 Q= R3 R2 1+ 1+ R2 R4
R4 R3 R2 HP/N S BP LP VIN R1 CC
R2
R4 R4 -R2 HOLP = R1 R4 + R2 HOBP =
-R 3
+
-
COM
R1
HON1( f 0Hz) =
-R2
R4 R1 R4 + R2
-R2
Figure 4. Mode 2, 2nd-Order Filter Providing a Highpass Notch, Bandpass, and Lowpass Outputs
Mode 2N Design Equations f fO = CLK 100 f fn = CLK 100 Q= R3 R2 1+ R2 R4
HON2 (at f = fCLK / 2) =
R1
Mode 2N Figure 5 shows the configuration of Mode 2N. This mode extends the topology of Mode 3A to Mode 2, where the highpass and lowpass outputs are summed through two external resistors, RH and RL, to create a lowpass notch filter that has higher frequency than the one in Mode 2. Mode 2 is most useful in lowpass elliptic designs. When cascading the sections of the MAX7490/MAX7491, the highpass and lowpass outputs can be summed directly into the inverting input of the next section. Only one external op amp is needed.
CC R4 R3 R2 HP/N R1 VIN S
R 1+ H RL R2 R4 R2 R4 R1 R4 + R2
1+
R R HON1(f 0Hz) = G + G RH RL
BP
LP
+
-
RH
RL
RG
COM
LOWPASS NOTCH OUTPUT
COM
Figure 5. Mode 2N, 2nd-Order Filter Providing a Lowpass Notch Output
12 ______________________________________________________________________________________
Dual Universal Switched-Capacitor Filters MAX7490/MAX7491
Mode 3 Figure 6 shows the configuration of Mode 3. This mode is a sampled time (Z transform) equivalent of the classical 2nd-order state variable filter. In this versatile mode, the ratio of resistors R2 and R4 can move the center frequency both above and below the nominal ratio. Mode 3 is commonly used to make multiple-pole Chebyshev filters with a single clock frequency. This mode can also be used to make high-order all-pole bandpass, lowpass, and highpass filters. Mode 3 Design Equations
f fO = CLK 100 Q= R2 R4
CC R4 R3 R2 HP VIN R1 S COM BP LP
+
-
COM
R3 R2 R2 R4 -R2 HOHP = R1 -R4 HOLP = R1 -R3 HOBP = R1
Figure 6. Mode 3, 2nd-Order Section Providing Highpass, Bandpass, and Lowpass Outputs
Mode 3A Figure 7 shows the configuration of Mode 3A. Similar to Mode 2, this mode adds an external op amp. See Table 3 for op amp selection ideas. This op amp creates a highpass notch and lowpass notch by summing
the highpass and lowpass outputs through two external resistors, RH and RL. The ratio of resistors RH and RL adjusts the notch frequency, while R2 and R4 adjust the bandpass center frequency, since the notch (zero pair) frequency can be adjusted to both above and below fO. Mode 3A is suitable for both lowpass and highpass elliptic or Cauer filters. In multipole elliptic filters, only one external op amp is needed. Use the inverting input of the internal op amp as the summing node for all but the final section of the filter.
CC R4 R3 R2 N/HP R1 VIN S COM BP LP
+
-
RL
RG
COM
RH
LOWPASS NOTCH OUTPUT
COM
Figure 7. Mode 3A, 2nd-Order Filter Providing Highpass Notch or Lowpass Notch Outputs
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13
Dual Universal Switched-Capacitor Filters MAX7490/MAX7491
Table 3. Suggested External Op Amps
PART MAX4281 MAX4322 MAX4130 MAX4490 GBW (MHz) 2 5 10 10 SLEW RATE (V/s) 0.7 2.0 4.0 10.0 ISUPPLY/AMP (mA) 0.5 1.1 1.15 2.0 PIN-PACKAGE 5 SOT23 5 SOT23 5 SOT23 5 SOT23
Mode 3A Design Equations f fO = CLK 100 f fn = CLK 100 Q= R3 R2 R2 R4 RH RL R2 R4 -R2 R1
-R4
Offset Voltage
Switched-capacitor integrators generally exhibit higher input offsets than discrete RC integrators. The larger offset is mainly due to the charge injection of the CMOS switches into the integrating capacitors. The internal op amp offset also adds to the overall offset value. Figure 8 shows the input offsets from a single 2nd-order section. Table 4 lists the formula for the output offset voltage for various modes and output pins.
Power Supplies
The MAX7490 operates from a single +5V supply, and the MAX7491 operates from a single +3V supply. Bypass VDD to GND with at least a 0.1F capacitor. VDD should be isolated from other digital or high-voltage analog supplies. If dual supplies are required, connect the COM pin to the system ground and the GND pin to the negative supply. Figure 9 shows an example of dual-supply operation. Single-supply and dual-supply performances are equivalent. For dual-supply operation, drive CLK, SHDN, and EXTCLK from GND (which is now V-) to VDD. If using the internal oscillator in dualsupply mode, COSC can be returned to either GND or the actual ground voltage. Use the MAX7490 for 2.5V and use the MAX7491 for 1.5V. For most applications, a 0.1F bypass capacitor from COM to GND is sufficient. If the VDD supply has significant 60Hz energy, increase this capacitor to 1F or greater to provide better power-supply rejection.
HOHP = HOLP = HOBP =
R1
-R 3
R1
HON1(f 0Hz) =
RG R4 RL R1 RG R2 RH R1
HON2 (at f = fCLK / 2) =
Note: When the passband gain error exceeds 1dB, the use of capacitor CC between the lowpass output and the inverting input will reduce the gain error. The value can best be determined experimentally. Typically, it should be about 5pF/dB (CC-MAX = 15pF).
INV
N/HP VOS1
BP
LP
+
COM
S
VOS2
VOS3
Figure 8. Block Diagram of a 2nd-Order Section Showing the Input Offsets
14 ______________________________________________________________________________________
Dual Universal Switched-Capacitor Filters MAX7490/MAX7491
Table 4. Output DC Offsets for a 2nd-Order Section
MODE 1 1b VOSN/HP VOS1[1 + (R2 / R3) + (R2 / R1)] - (VOS3) (R2 / R3) VOS1[1 + (R2 / R3) + (R2 / R1)] - (VOS3) (R2 / R3) VOS1[1 + (R2 / R3) + (R2 / R1) + (R2 / R4) (VOS3)(R2 / R3)][R4 / R2 + R4] + (VOS2)[R2 / R2 + R4] VOS2 VOSBP VOS3 VOS3 VOSN/HP - VOS2 (VOSN/HP - VOS2)[1 + R5 / R6)] VOSLP
2
VOS3
VOSN/HP - VOS2 VOS1[1 + (R4 / R1) + (R4 / R2) + (R4 / R3)] - (VOS2) (R4 / R2) - (VOS3)(R4 / R3)
3
VOS3
Aliasing
V+
VDD
* SHDN
0.1F
COM
V+ V-
CLOCK
CLK
MAX7490 MAX7491
0.1F GND
*DRIVE SHDN TO V- FOR LOW-POWER SHUTDOWN MODE.
V-
Figure 9. Dual-Supply Operation
Input Signal Amplitude Range
The optimal input signal range is determined by observing the voltage level at which the signal-to-noise plus distortion (SINAD) ratio is maximized for a given corner frequency. The Typical Operating Characteristics show the THD + Noise response as the input signal's peak-to-peak amplitude is varied. In most systems, the input signal should be kept as large as possible to maximize the signal-to-noise ratio (SNR). Allow sufficient headroom to ensure no signal clipping under expected operating conditions.
Aliasing is an inherent phenomenon of most switchedcapacitor filters. As with all sampled systems, frequency components of the input signal above one half the sampling rate will be aliased. The MAX7490/MAX7491 sample at twice the clock frequency, yielding a 200:1 sampling to cutoff frequency ratio. In particular, input signal components (fIN) near the sampling rate generate a difference frequency (fSAMPLING - fIN) that often falls within the passband of the filter. Such aliased signals, when they appear at the output, are indistinguishable from real input information. For example, the aliased output signal generated when a 99kHz waveform is applied to a filter sampling at 100kHz, (fCLK = 50kHz) is 1kHz. This waveform is an attenuated version of the output that would result from a true 1kHz input. Since sampling is done at twice the clock frequency, the Nyquist frequency is the same as the clock frequency. A simple passive RC lowpass input filter is usually sufficient to remove input frequencies that can be aliased. In many cases, the input signal itself may be band limited and require no special anti-alias filtering. Selecting a passive filter cutoff frequency equal to fC/2 gives 12dB rejection at the Nyquist frequency.
Clock Feedthrough
Clock feedthrough is defined as the RMS value of the clock frequency and its harmonics that are present at the filter's output pins, even without input signal. The clock feedthrough can be greatly reduced by adding a simple RC lowpass network at the final filter output. Choose a cutoff frequency as low as possible to provide maximum noise attenuation. The attenuation and phase shift of the external filter will limit the actual frequency selected.
Anti-Aliasing and Post-DAC Filtering
When using the MAX7490/MAX7491 for anti-aliasing or post-DAC filtering, synchronize the DAC (or ADC) and the filter clocks. If the clocks are not synchronized, beat frequencies may alias into the desired passband.
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15
Dual Universal Switched-Capacitor Filters MAX7490/MAX7491
Table 5. Cascading Identical Bandpass Filter Sections
TOTAL SECTIONS 1 2 3 4 5 TOTAL BW 1.000 B 0.644 B 0.510 B 0.435 B 0.386 B TOTAL Q 1.00 Q 1.55 Q 1.96 Q 2.30 Q 2.60 Q
Multiple Filter Stages
In some designs, such as very narrow band filters, or in modes where fO cannot be tuned with resistors, several 2nd-order sections with identical fO may be cascaded without multiple feedback. The total Q of the resultant filter (QT) is: Total QT = Q / (2
1/ N
- 1)
1/ 2
Wideband Noise
The wideband noise of the filter is the total RMS value of the device's noise spectral density and is used to determine the operating SNR. Most of its frequency contents lie within the filter's passband and cannot be reduced with postfiltering. The total noise depends mainly on the Q of each filter section and the cascade sequence. Therefore, in multistage filters, place the section with the highest Q first for lower output noise.
Q is the Q of each individual filter section, and N is the number of 2nd-order sections. In Table 5, the total Q and total bandwidth (BW) are listed for up to five identical 2nd-order sections. B is the bandwidth of each section.
Chip Information
PROCESS: BiCMOS
16
______________________________________________________________________________________
Dual Universal Switched-Capacitor Filters
Typical Application Circuit
4TH-ORDER 10kHz BANDPASS FILTER R1B 200k
MAX7490/MAX7491
R3A 200k R2A 10k R1 200k VIN
LPA BPA
LPB R3B 200k BPB
OUT 5 0 -5 -10 GAIN (dB)
4TH-ORDER 10kHz BANDPASS FILTER FREQUENCY RESPONSE
NA/HPA INVA SA SHDN GND
MAX7490 MAX7491
R2B 10k NB/HPB INVB SB COM EXTCLK CLK fCLK = 1MHz C2 0.1F
-15 -20 -25 -30 -35 -40 8 9 10 FREQUENCY (kHz) 11 12
VDD C1 0.1F
VDD
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 16 QSOP PACKAGE CODE E16+4 DOCUMENT NO. 21-0055
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17
Dual Universal Switched-Capacitor Filters MAX7490/MAX7491
Revision History
REVISION NUMBER 0 1 REVISION DATE 7/00 4/09 Initial release Changes to add lead-free packages, style edits DESCRIPTION PAGES CHANGED -- 1-10, 16, 17, 18
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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